The present invention relates to a clock recovery circuit for synchronizing the reception of a serial digital transmission.
For the synchronous (or even asynchronous) transmission of a serial digital data signal, the sending unit includes a generator of a serial clock signal used for coding and serializing the data. So as to synchronize correctly the decoding and deserializing of the received data, the receiving unit must also include a clock signal generator, the value of the frequency of which is a faithful image of the actual line bit-rate on the transmission channel. The clock signal generator of the receiving unit comprises a phase-locked loop (PLL) whose voltage-controlled oscillator provides a clock signal reproducing the frequency of the bit rate of the received data signal. Usually, the coding of the data is of NRZ or NRZI type, which, apart from the advantage of producing a signal having a minimum useful passband and a stable line mean value, achieves a sizeable density of transitions so as to facilitate phase-locking on reception. However, sequences may survive during which the signal received exhibits few transitions, making phase-locking on reception very difficult or even impossible. Since the pull-in range of this locking is then directly proportional to the density of transitions of the data signal received, it is seen that it is necessary for the voltage-controlled oscillator to oscillate at an initial frequency very similar to that to be extracted.
It is appreciated that it is difficult to construct a voltage-controlled oscillator having characteristics specified with a high degree of accuracy. The variations resulting from the manufacturing process and the in-service temperature variations introduce an uncertainty as regards the precise values of the characteristic parameters. On the other hand, integration techniques make it possible to construct, within the same integrated circuit, two oscillators having very similar characteristics.
This well-known principle has already been exploited in order to construct clock recovery circuits using two integrated and identical oscillators, by the master and slave technique. For example, the article "A BiCMOS Receive/Transmit PLL Pair for Serial Data Communication" by B. L. Thompson and H. S. Lee, published in Proc. of the IEEE Custom Integrated Circuits Conference, 1992, pages 29.6.1-29.6.5, describes a circuit containing matched master and slave oscillators. The master oscillator forms part of a frequency synthesis loop. Its output frequency, divided by N, is compared with a reference frequency provided by a quartz. The control voltage for the master oscillator is obtained by low-pass filtering of the signal representing the difference of the compared frequencies. The slave oscillator forms part of a phase tracking loop. The phase of its output signal is compared with that of the received data signal. The difference of the compared phases is subjected to low-pass filtering so as to provide a fine correction voltage. This fine correction voltage is superimposed on the control voltage for the master oscillator to form the control voltage for the slave oscillator. The output signal from the slave oscillator constitutes the recovered clock signal.
A drawback of the above clock recovery circuit is the fact that permanent application of the master oscillator's control voltage to the input of the slave oscillator induces phase fluctuations in the recovered clock signal. Indeed, the comparator of the frequency synthesis loop is of the "phase/frequency" type and generates, when balanced, spurious pulses (glitches) at the reference frequency of the quartz which, even if integrated by the loop filter, modulate the retrieved clock frequency. This drawback is particularly substantial for high transmission frequencies (typically greater than 100 MHz), and worsens the jitter of the recovered clock.
An object of the invention is to propose a clock recovery circuit which meets the requirements of practice better than the previously known circuits, especially in the high-frequency region.